The present invention relates to a phase locked loop capable of controlling a bandwidth, and a method for controlling the same.
A phase locked loop (PLL) and a delay locked loop (DLL) are typical examples of a feedback system. The feedback system in a synchronous semiconductor memory device performs a data transfer with external devices, using an internal clock synchronized and locked to an external clock that is input from an external device such as a memory controller. To transfer data stably between the semiconductor memory device and a memory controller, synchronization of the data signal with a reference clock is very important.
The PLL feedback system includes a phase/frequency detector, a charge pump, a loop filter and a voltage controlled oscillator (VCO) to change frequency of a clock input to the PLL feedback system. The phase/frequency detector compares a phase of the input clock with a phase of a feedback clock to generate an up signal or a down signal depending on a phase difference between the clocks. The charge pump outputs a current corresponding to the up signal or the down signal. The loop filter smoothes the current to generate a voltage. The voltage controlled oscillator generates a clock of a frequency corresponding to the input voltage.
A typical PLL system having the above described configuration filters a high frequency jitter component of an applied reference clock (or an input clock) to reduce a jitter component in a clock to be output.
FIG. 1 is a graph illustrating a functional relation of a PLL output jitter to a reference clock jitter versus an input jitter frequency in an ideal PLL system. The ideal PLL system serves as a low pass filter for removing high frequency jitter components having a frequency above a PLL bandwidth among the jitter components of the input clock (reference clock) while maintaining low frequency jitter components as they are.
The low pass filter of the typical PLL system generally has a certain bandwidth. However, because of the characteristics of the PLL system including a feedback loop, a phase margin may not be secured sufficiently. In that case, a peaking phenomenon rather increasing the reference jitter components may occur, as shown in FIG. 2.
In addition, the jitter peaking phenomenon may also occur even when a power noise near the bandwidth of the PLL system is applied, as shown in FIG. 3. Therefore, when a low jitter characteristic is required by the PLL system, the PLL system should have a bandwidth out of a frequency region of a maximum power noise or of a high reference clock jitter.
FIG. 4 is a circuit diagram illustrating a charge pump for determining a bandwidth in a typical PLL system. Referring to FIG. 4, the charge pump includes a first switch and a second switch operating in response to up/down signals provided by a phase/frequency detector, and a capacitor C3 connected to an output node between the first and second switches. The first and second switches include a switch type transistor for outputting the up/down signals.
The charge pump having the above described configurations charges/discharges the capacitor by a constant current Icp in response to the constant up/down signals applied to the first and second switches, to determine a control voltage of a voltage controlling oscillator. In other words, the charge pump allows a constant current to flow to the capacitor C3 in response to the applied up or down signal. Therefore, the charge pump consists of only one current source, and the current source has only one bandwidth in the PLL system.
As described above, in order to reduce jitter components, the PLL system should have a bandwidth out of a frequency region of a maximum power noise or of a high reference clock jitter. However, in a general purpose PLL system used in a variety of systems, it is difficult to select an appropriate PLL bandwidth excluding all the frequency regions of a maximum power noise or of a high reference clock jitter because they are different in different systems.